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ZL38002 Low-Voltage Acoustic Echo Canceller with Noise Reduction
Data Sheet Features
* * * * * * * * * * * * * * 112 ms acoustic echo canceller Up to 12 dB of noise reduction Works with low cost voice codec. ITU-T G.711 or signed mag /A-Law, or linear 2's compliment Each port may operate independently in companded format or linear format Advanced NLP design - full duplex speech with no switched loss on audio paths Fast re-convergence time: tracks changing echo environment quickly Adaptation algorithm converges even during Double-Talk Designed for exceptional performance in high background noise environments Provides protection against narrow-band signal divergence Howling prevention stops uncontrolled oscillation in high loop gain conditions Programmable offset nulling of all PCM channels Serial micro-controller interface Idle channel noise suppression ST-BUS, GCI, or variable-rate SSI PCM interfaces * * * * * * * * * Ordering Information ZL38002QDG 48 Pin TQFP ZL38002QDG1 48 Pin TQFP* ZL38002DGA1 36 Pin QSOP* ZL38002DGB1 36 Pin QSOP* * Pb Free Matte Tin -40C to 85C User gain control provided for speaker path (-24 dB to +21 dB in 3 dB steps) Adjustable gain pads from -24 dB to +21 dB at Xin, Sin and Sout to compensate for different system requirements AGC on speaker path Handles up to -6 dB acoustic echo return loss (with the appropriate gain pad settings) Transparent data transfer and mute options 20 MHz master clock operation Low power mode during PCM Bypass Bootloadable for future factory software upgrades 2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs Trays Trays Tubes Tape and Reel
August 2005
Limiter Sin MD1 NBSD CONTROL Adaptive Filter UNIT Double Talk Detector R1 R1 NBSD
Program ROM Program RAM
/A-Law/
Linear
HP Filter
Gain Pad
S1 +
+
-
S2
ADV NLP
Noise Reduction
Gain Pad
Linear/ /A-Law
Sout DATA1 DATA2
ACOUSTIC ECHO PATH
Micro Interface
Gain Pad
Howling Controller
MD2 Rout Linear/ /A-Law
Limiter
SCLK
-24 -> +21dB
CS HP Filter /A-Law/
Linear
AGC
User Gain
Rin
VDD
VSS
RESET
FORMAT
ENA2
ENA1
LAW
F0i
BCLK/C4i
MCLK
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL38002
Applications
* * * * * Hands free car kits Full duplex speaker-phone for digital telephone Echo cancellation for video conferencing Security systems Intercom systems (door entry, elevator, and restaurant drive-through)
Data Sheet
MCLK
Figure 2 - Pin Connections
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Zarlink Semiconductor Inc.
IC IC IC LAW NC FORMAT NC
ENA1 MD1 ENA2 MD2 Rin Sin IC MCLK IC IC IC LAW FORMAT RESET NC NC SCLK CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
QSOP
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
IC IC IC MCLK2 NC VSS VDD2
VSS2
IC IC BCLK/C4i F0i Rout Sout VDD NC DATA1 DATA2
NC MCLK2 IC IC IC NC ENA1 NC MD1 ENA2 MD2 Rin
36 38
NC VSS VDD2 VSS2 NC IC IC BCLK/C4i NC F0i Rout NC 34 32 30 28 26 24 22 40 20 42 44 16 46 14 48 2 4 6 8 10 12
TQFP
18
Sout VDD NC DATA1 NC DATA2 NC CS SCLK NC NC RESETB
NC Sin IC NC
ZL38002
Pin Description QSOP Pin # 1 TQFP Pin # 43 Name ENA1 Description
Data Sheet
SSI Enable Strobe/ST-BUS & GCI Mode for Rin/Sout (Input). This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present for frame synchronization. This is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for on Rin/Sout pins. Strobe period is 125 ms. For STBUS or GCI, this pin, in conjunction with the MD1 pin, selects the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI operation, this pin, in conjunction with the ENA1 pin, will select the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode. SSI Enable Strobe /ST-BUS & GCI Mode for Sin/Rout (Input). This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer on Sin/Rout pins. Strobe period is 125 ms. For ST-BUS/GCI, this pin, in conjunction with the MD2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI operation, this pin in conjunction with the ENA2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode. Receive PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input stream. Data may be in either companded or 2's complement linear format. This is the Receive Input channel from the line (or network) side. Data bits are clocked in following SSI, GCI or ST-BUS timing requirements. Send PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input stream. Data may be in either companded or 2's complement linear format. This is the Send Input channel (from the microphone). Data bits are clocked in following SSI, GCI or ST-BUS timing requirements. Internal Connection (Input). Must be tied to Vss. Master Clock (Input). Nominal 20 MHz Master Clock input (can be asynchronous relative to 8 KHz frame signal.) Tie together with MCLK2. Internal Connection (Input). Must be tied to Vss. A/ Law Select (Input). When low, selects -Law companded PCM. When high, selects A-Law companded PCM. This control is for both serial pcm ports.
2
45
MD1
3
46
ENA2
4
47
MD2
5
48
Rin
6
2
Sin
7 8 9,10,11 12
3 5 6, 7, 8 9
IC MCLK IC LAW
13
11
FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM code. This control is for both serial pcm ports. RESET SCLK Reset / Power-down (Input). An active low resets the device and puts the ZL38002 into a low-power stand-by mode. Serial Port Synchronous Clock (Input). Data clock for the serial microport interface.
14 17
13 16
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Zarlink Semiconductor Inc.
ZL38002
Pin Description (continued) QSOP Pin # 18 19 TQFP Pin # 17 19 Name CS DATA2 Description
Data Sheet
Serial Port Chip Select (Input). Enables serial microport interface data transfers. Active low. Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd. Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1 pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for transmitting and receiving data. Positive Power Supply (Input). Nominally 3.3 volts. Send PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM output stream. Data may be in either companded or 2's complement linear PCM format. This is the Send Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked out following SSI, STBUS or GCI timing requirements. Receive PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM output stream. Data may be in either companded or 2's complement linear PCM format. This is the Receive out signal after the AGC and gain control. Data bits are clocked out following SSI, ST-BUS or GCI timing requirements. Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low (or active-high) frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss.
20
21
DATA1
22 23
23 24
VDD Sout
24
26
Rout
25
27
F0i
26
29
BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit clock. This clock must be synchronous with ENA1 and ENA2 enable strobes. In ST-BUS or GCI operation, C4i pin must be connected to the 4.096 MHz (C4) system clock. IC VSS2 VDD2 VSS MCLK2 IC NC Internal Connection (Input). Tie to Vss. Digital Ground (Input). Nominally 0 volts. Positive Power Supply (Input). Nominally 3.3 volts (tie together with VDD). Digital Ground (Input). Nominally 0 volts (tie together with VSS2). Master Clock (Input). Nominal 20 MHz master clock (tie together with MCLK). Internal Connection (Input). Tie to Vss. No Connect (Output). This pin should be left unconnected.
27, 28 29 30 31 33 34,35,36 15, 16, 21, 32
30, 31 33 34 35 38 39, 40, 41 1, 4, 10, 12, 14, 15, 18, 20, 22, 25, 28, 32, 36, 37, 42, 44
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Zarlink Semiconductor Inc.
ZL38002 Table of Contents
Data Sheet
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 Adaptation Speed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 Advanced Non-Linear Processor (ADV-NLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 Narrow Band Signal Detector (NBSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6 Howling Detector (HWLD)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.7 Programmable High Pass Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.8 Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.9 User Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.10 AGC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.11 Programmable Gain Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.12 Mute Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.13 Master Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.14 AEC Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.15 Adaptation Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.16 Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.17 Power Down / Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.0 PCM Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 ST-BUS and GCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 SSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 PCM Law and Format Control (LAW, FORMAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 Linear PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 Bit Clock (BCLK/C4i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 Master Clock (MCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.0 Microport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.0 Bootload Process and Execution from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.0 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.0 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Zarlink Semiconductor Inc.
ZL38002
1.0 Functional Description
Data Sheet
The ZL38002 device is comprised of an acoustic echo canceller and the necessary control functions for operation. The ZL38002 guarantees clear signal transmission in both transmit and receive audio path directions to ensure reliable voice communication, even when low level signals are provided. The ZL38002 does not use variable attenuators during double-talk or single-talk periods of speech, as do many other acoustic echo cancellers for speakerphones. Instead, the ZL38002 provides high performance full-duplex operation similar to network echo cancellers. This results in users experiencing clear speech and uninterrupted background signals during the conversation and prevents subjective sound quality problems associated with "noise gating" or "noise contrasting". The ZL38002 uses an advanced adaptive filter algorithm that is double-talk stable, which means that convergence takes place even while both parties are talking. This algorithm allows continual tracking of changes in the echo path, regardless of double-talk, as long as a reference signal is available for the echo canceller. The echo tail cancellation capability of the acoustic echo canceller has been sized appropriately (112 ms) to cancel echo in an average sized office with a reverberation time of less than 112 ms. In addition to the echo cancellers, the following functions are supported: * * * * * * * * * * * * 12 dB of noise reduction User gain pads at the Sin and Sout ports plus one at the input of adaptive filter (XRAM) Control of adaptive filter convergence speed during periods of double-talk, far end single-talk and near-end echo path changes Control of Non-Linear Processor thresholds for suppression of residual non-linear echo Howling detector to identify when instability is starting to occur and to take action to prevent oscillation Narrow-Band Detector for preventing adaptive filter divergence caused by narrow-band signals Programmable high pass filters at Rin and Sin for removal of DC components in PCM channels Limiters that introduce controlled saturation levels Serial controller interface compatible with Motorola, National and Intel microcontrollers PCM encoder/decoder compatible with m/A-Law ITU-T G.711, m/A-Law Sign-Mag or linear 2's complement coding Automatic gain control on the receive speaker path Idle channel noise suppression
1.1
Noise Reduction
The ZL38002 incorporates a noise reduction circuit that reduces background noise up to 12 dB. The level of noise reduction is programmed allowing the user to adjust the level of noise cancellation according to system requirements. This is controlled through the NR register on page 3 address 16H. A larger value in this register will increase the amount of noise reduction. As the amount of noise reduction is increased the amount of distortion in the audio path also increases. The noise reduction can be bypassed by setting bit 4 in Control Register 1 (Address 01H)
1.2
Noise Suppression
The ZL38002 also utilizes noise suppression which can be used to reduce idle channel noise from emanating from the acoustic end. By setting a threshold value in the lower nibble (bits 0-3) of the MCR2 register on page 0 address 01H, idle channel noise below the threshold is zero-forced. The threshold limits ranges from 0 to 16 (based on a 16 bit 2's complement) with a value of 0 disabling suppression.
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Zarlink Semiconductor Inc.
ZL38002
1.3 Adaptation Speed Control
Data Sheet
The adaptation speed of the acoustic echo canceller is designed to optimize the convergence speed versus divergence caused by interfering near-end signals. Adaptation speed algorithm takes into account many different factors such as relative double-talk condition, far end signal power, echo path change and noise levels to achieve fast convergence.
1.4
Advanced Non-Linear Processor (ADV-NLP)
After echo cancellation, there is likely to be residual echo which needs to be removed so that it will not be audible. The ZL38002 uses an NLP to remove low level residual echo signals which are not comprised of background noise. The operation of the NLP depends upon a dynamic activation threshold, as well as a double-talk detector which disables the NLP during double-talk periods. The ZL38002 keeps the perceived noise level constant, without the need for any variable attenuators or gain switching that causes audible "noise gating". The noise level is constant and identical to the original background noise even when the NLP is activated. The NLP can be disabled by setting the NLP- bit to 1 in the AEC control registers.
1.5
Narrow Band Signal Detector (NBSD)1
Single or multi-frequency tones (e.g,. DTMF, or signalling tones) present in the reference input of an echo canceller for a prolonged period of time may cause the adaptive filter to diverge. The Narrow Band Signal Detector (NBSD) is designed to prevent this divergence by detecting single or multi-tones of arbitrary frequency, phase, and amplitude. When narrow band signals are detected, the filter adaptation process is stopped but the echo canceller continues to cancel echo. The NBSD can be disabled by setting the NB- bit to 1 in the MC control registers.
1.6
Howling Detector (HWLD)1
The Howling detector is part of an Anti-Howling control, designed to prevent oscillation as a result of positive feedback in the audio paths. The HWLD can be disabled by setting the AH- bit to 1 in the (MC) control register.
1.7
Programmable High Pass Filter
Programmable high pass filters are place at the Sin and Rin ports. These filters have two functions, one to remove any DC offset that may be present on either the Rin or the Sin port and two, to filter low frequency noise such as road noise (below 300 Hz). The offset null filters can be disabled by setting the HPF- bit to 1 in the AEC control registers.
1.8
Limiters
To prevent clipping in the echo paths, two limiters with variable thresholds are provided at the outputs.
1.9
User Gain
The user gain function provides the ability for users to adjust the audio gain on all paths. This gain is adjustable from -24 dB to +21 dB in 3 dB steps for the Sout and Rout paths. It is important to use ONLY this user gain function to adjust the speaker volume. The user gain function in the ZL38002 is optimally placed outside the echo path such
1. Patented
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Zarlink Semiconductor Inc.
ZL38002
Data Sheet
that no reconvergence is necessary after gain changes, avoiding a burst of each overtime the speaker gain is changed.
1.10
AGC
The AGC function is provided to limit the volume in the speaker path. The gain of the speaker path is automatically reduced during the following conditions: * * * When clipping of the receive signal occurs When initial convergence of the acoustic echo canceller detects unusually large echo return When howling is detected
The AGC can be disabled by setting the AGC- bit to 1 in MC control register
1.11
Programmable Gain Pad
The ZL38002 has three gain pads located at Sin, Sout and at the adaptive filter (Xin). These gain pads are intended to be set once during initialization and not be used as dynamic gain adjustments. The purpose of theses gainpads are to help fine tune the performance of the acoustic echo canceller for a particular system. For example, the gain pad can be used to improve the subjective quality in low ERL environments. The ZL38002 can cancel echo with a ERL as low as 0 dB (attenuation from Rout to Sin). In many hand free applications, the ERL can be low (or negative). This is due to both speaker and microphone gain setting. The speaker gain has to be set high enough for the speaker to be heard properly and the microphone gain needs to be set high enough to ensure sufficient signal is sent to the far end. If the ERL (Acoustic Attenuation - speaker gain - microphone gain) is greater than 0 dB, then the echo canceller cannot cancel echo. To overcome this limitation, the gain pad at Sin and Sout can be used to lower the Sin level (and therefore the ERL) by 6 dB, perform the echo cancellation then amplify it at Sout by 6 dB. This will have the effect having 0dB gain between Sin and Sout for double talk signals while injecting a additional 6 dB attenuation for the echo return. It is important to reduce the DTDT threshold (Page 0 address 30) to match the Sin/Sout gain settings. The gain can be accessed through Customer Gain Control Registers 1 - 2 (Page 0, Address 1CH - 1DH).
1.12
Mute Function
A pcm mute function is provided for independent control of the Receive and Send audio paths. Setting the MUTE_R or MUTE_S bit in the MC register, causes quiet code to be transmitted on the Rout or Sout paths respectively. The ZL38002 has an optional DC offset control. The user can add a positive offset to the mute value. This is controlled through the DC offset register (Page 0, Address 03h) Quiet code is defined according to the following table. LINEAR 16 bits 2's complement +Zero (quiet code) 0000h SIGN/ MAGNITUDE -Law A-Law 80h CCITT (G.711) -Law A-Law
FFh
D5h
Table 1 - Quiet PCM Code Assignment
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Zarlink Semiconductor Inc.
ZL38002
1.13 Master Bypass
Data Sheet
A PCM bypass function is provided to allow transparent transmission of pcm data through the ZL38002. When the bypass function is active, PCM data passes transparently from Rin to Rout and from Sin to Sout, with bit-wise integrity preserved. When the Bypass function is selected, most internal functions are powered down to provide low power consumption. The BYPASS control bit is located in the main control MC register.
1.14
AEC Bypass
An AEC bypass function is provided to allow the user to bypass only the AEC (i.e the echo estimate from the adaptive filter is not subtracted from the Send path). This bypass does not effect any other function in the ZL38002. The AEC BYPASS control bit is located in the Acoustic Echo Canceller Control Register (AECCR).
1.15
Adaptation Control
Adaptation control bit is located in the Acoustic Echo Canceller Control Register (Page 0, Address 21h). When the ADAPT- bit is set to 1, the adaptive filter is frozen at the current state. In this state, the device continues to cancel echo with the current echo model. When the ADAPT- bit is set to 0, the adaptive filter is continually updated allowing the echo cancellor to adapt and track changes in the echo path. This is the normal operating state ZL38002
1.16
Throughput Delay
In all modes, except ST-BUS/GCI operation, voice channels have 2 frames of constant delay. In ST-BUS/GCI operation, the D and C channels have a delay of one frame.
1.17
Power Down / Reset
Holding the RESET pin at logic low will keep the ZL38002 device in a power-down state. In this state all internal clocks are halted, and the DATA1, Sout and Rout pins are tristated. The user should hold the RESET pin low for at least 200 msec following power-up. This will insure that the device powers up in a proper state. Following any return of RESET to logic high, the user must wait for 8 complete 8 KHz frames prior to writing to the device registers. During this time, the initialization routines will execute and set the ZL38002 to default operation based on the installed algorithm.
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Zarlink Semiconductor Inc.
ZL38002
2.0 PCM Data I/O
Data Sheet
The PCM data transfer for the ZL38002 is provided through two PCM ports. One port consists of Rin and Sout pins while the second port consists of Sin and Rout pins. The data are transferred through these ports according to either ST-BUS, GCI or SSI conventions detected automatically by the device. The ZL38002 determines the convention by monitoring the signal applied to the F0i pin. When a valid ST-BUS (active low) frame pulse is applied to the F0i pin, the ZL38002 will assume ST-BUS operation. When a valid GCI (active high) frame pulse is applied to the F0i pin, the device will assume GCI operation. If F0i is tied continuously to Vss, the device is set to SSI operation. Figures 3 to 6 show timing diagrams of these 3 PCM-interface operation conventions.
2.1
ST-BUS and GCI Operation
The ST-BUS PCM interface conforms to Zarlink's ST-BUS standard with an active-low frame pulse. Input data is clocked in by the rising edge of the bit clock (C4i) three-quarters of the way into the bit cell and output data bit boundaries (Rout, Sout) occur every second falling edge of the bit clock (see Figure 11.) The GCI PCM interface corresponds to the GCI standard commonly used in Europe with an active-high frame pulse. Input data is clocked in by the falling edge of the bit clock (C4i) three-quarters of the way into the bit cell and output data bit boundaries (Rout, Sout) occur every second rising edge of the bit clock (see Figure 12.) Either of these interfaces (ST-BUS or GCI) can be used to transport 8 bit companded PCM data (using one timeslot) or 16 bit 2's complement linear PCM data (using two timeslots). The MD1/ENA1 pins select the timeslot on the Rin/Sout port while the MD2/ENA2 pin selects the timeslot on the Sin/Rout port, as in Table 2. Figures 3 to 6 illustrate the timeslot allocation for each of these four modes.
C4i start of frame (stbus & GCI) F0i (ST-BUS)
0
1
2
3
4
B
F0i (GCI) PORT1 Rin
76 543210 EC
Sout PORT2 Sin
76 543210
76 543210 EC
Rout
76 543210
outputs = High impedance inputs = don't care
In ST-BUS/GCI Mode 1, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 0. Note that the user can configure PORT1 and PORT2 into different modes.
Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1)
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Zarlink Semiconductor Inc.
ZL38002
C4i start of frame (stbus & GCI) F0i (ST-BUS)
Data Sheet
0
1
2
3
4
B
F0i (GCI) PORT1 Rin
76543210 EC
Sout
76 543210
PORT2 Sin
76543210 EC
Rout outputs = High impedance inputs = don't care
76543210
In ST-BUS/GCI Mode 2, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 2. Note that the user can configure PORT1 and PORT2 into different modes.
Figure 4 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 2 (Mode 2)
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C4i start of frame (stbus & GCI) F0i (ST-BUS)
Data Sheet
0
1
2
3
4
D
F0i (GCI) PORT1 Rin
C
B
765432107654321076543210 EC
Sout
765432107654321076543210
PORT2 Sin
765432107654321076543210 EC
Rout
765432107654321076543210
outputs = High impedance inputs = don't care indicates that an input channel is bypassed to an output channel
ST-BUS/GCI Mode 3 supports connection to 2 B+D devices where timeslots 0 and 1 transport D and C channels and echo canceller (EC) I/O channels are assigned to ST-BUS timeslot 2 (B). Both PORT1 and PORT2 must be configured in Mode 3.
Figure 5 - ST-BUS and GCI 8-Bit Companded PCM I/O with D and C channels (Mode 3)
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C4i start of frame (stbus & GCI) F0i (stbus)
Data Sheet
F0i (GCI) Rin PORT1 Sout
S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 EC S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
Sin PORT2 Rout
S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 EC S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
outputs = High impedance inputs = don't care
ST-BUS/GCI Mode 4 allows 16 bit 2's complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and PORT2 need not necessarily both be in mode 4.
Figure 6 - ST-BUS and GCI 16-Bit 2's Complement Linear PCM I/O (Mode 4)
PORT1 Rin/Sout Enable Pins MD1 0 0 1 1 ENA1 0 1 0 1
ST-BUS/GCI Mode Selection
PORT2 Sin/Rout Enable Pins MD2 ENA2 0 1 0 1
Mode 1. 8 bit companded PCM I/O on timeslot 0 Mode 2. 8 bit companded PCM I/O on timeslot 2. Mode 3. 8 bit companded PCM I/O on timeslot 2. Includes D & C channel bypass in timeslots 0 & 1. Mode 4. 16-bit 2's complement linear PCM I/O on timeslots 0 & 1. Table 2 - ST-BUS & GCI Mode Select
0 0 1 1
2.2
SSI Operation
The SSI PCM interface consists of data input pins (Rin, Sin), data output pins (Sout, Rout), a variable rate bit clock (BCLK), and two enable pins (ENA1, ENA2) to provide strobes for data transfers. The active high enable may be either 8 or 16 BCLK cycles in duration. Automatic detection of the data type (8 bit companded or 16-bit 2's complement linear) is accomplished internally. The data type cannot change dynamically from one frame to the next.
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Data Sheet
In SSI operation, the frame boundary is determined by the rising edge of the ENA1 enable strobe (see Figure 7). The other enable strobe (ENA2) is used for parsing input/output data and it must pulse within 125 microseconds of the rising edge of ENA1. In SSI operation, the enable strobes may be a mixed combination of 8 or 16 BCLK cycles allowing the flexibility to mix 2's complement linear data on one port (e.g., Rin/Sout) with companded data on the other port (e.g., Sin/Rout). Enable Strobe Pin ENA1 ENA2 Designated PCM I/O Port Line Side Echo Path (PORT 1) Acoustic Side Echo Path (PORT 2) Table 3 - SSI Enable Strobe Pins
2.3
PCM Law and Format Control (LAW, FORMAT)
The PCM companding/coding law used by the ZL38002 is controlled through the LAW and FORMAT pins. ITU-T G.711 companding curves for m-Law and A-Law are selected by the LAW pin. PCM coding ITU-T G.711 and SignMagnitude are selected by the FORMAT pin. See Table 4.
BCLK start of frame (SSI)
PORT1 ENA1
Rin
8 or 16 bits
EC
Sout 8 or 16 bits
PORT2 ENA2
Sin
8 or 16 bits
EC
Rout outputs = High impedance inputs = don't care Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate with 16-bit enable strobes. 8 or 16 bits
Figure 7 - SSI Operations
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Sign-Magnitude FORMAT=0 PCM Code /A-LAW LAW = 0 or 1 + Full Scale + Zero - Zero - Full Scale 1111 1111 1000 0000 0000 0000 0111 1111 ITU-T (G.711) FORMAT=1 -LAW LAW = 0 1000 0000 1111 1111 0111 1111 0000 0000 A-LAW LAW =1 1010 1010 1101 0101 0101 0101 0010 1010
Data Sheet
Table 4 - Companded PCM
2.4
Linear PCM
The 16-bit 2's complement PCM linear coding permits a dynamic range beyond that which is specified in ITU-T G.711 for companded PCM. The echo-cancellation algorithm will accept 16-bits 2's complement linear code which gives a maximum signal level of +15 dBm0.
2.5
Bit Clock (BCLK/C4i)
The BCLK/C4i pin is used to clock the PCM data for GCI and ST-BUS (C4i) interfaces, as well as for the SSI (BCLK) interface. In SSI operation, the bit rate is determined by the BCLK frequency. This input must contain either eight or sixteen clock cycles within the valid enable strobe window. BCLK may be any rate between 128 KHz to 4.096 MHz and can be discontinuous outside of the enable strobe windows defined by ENA1, ENA2 pins. Incoming PCM data (Rin, Sin) are sampled on the falling edge of BCLK while outgoing PCM data (Sout, Rout) are clocked out on the rising edge of BCLK. See Figure 13. In ST-BUS and GCI operation, connect the system C4 (4.096 MHz) clock to the C4i pin.
2.6
Master Clock (MCLK)
A nominal 20 MHz, continuously-running master clock (MCLK) is required. MCLK may be asynchronous with the 8 KHz frame.
3.0
Microport
The serial microport provides access to all ZL38002 internal read and write registers, plus write-only access to the bootloadable program RAM (see next section for bootload description). This microport is compatible with Intel MCS-51 (mode 0), Motorola SPI (CPOL=0, CPHA=0) and National Semiconductor Microwire specifications. The microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a synchronous data clock pin (SCLK). The ZL38002 automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National specifications. The microport dynamically senses the state of the SCLK pin each time the CS pin becomes active (i.e., high to low transition). If the SCLK pin is high during a CS activation, then the Intel mode 0 timing is assumed. In this case the DATA1 pin is defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during a CS activation, then Motorola/National timing is assumed and DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. The ZL38002 supports Motorola half-
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Data Sheet
duplex processor mode (CPOL=0 and CPHA=0). This means that during a write to the ZL38002, via a Motorola processor, output data from the DATA1 pin is disregarded. This also means that input data on the DATA2 pin is ignored by the ZL38002 during a valid read by the Motorola processor. All data transfers through the microport are two bytes long. This requires the transmission of a Command/Address byte followed by the data byte to be written to or read from the addressed register. CS must remain low for the duration of this two-byte transfer. As shown in Figures 8 and 9, the falling edge of CS indicates to the ZL38002 that a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the ZL38002 and the microcontroller. At the end of the two-byte transfer, CS is brought high again to terminate the session. The rising edge of CS will tri-state the DATA1 pin. The DATA1 pin will remain tri-stated as long as CS is high. Intel processors utilize Least Significant Bit (LSB) first transmission while Motorola/National processors use Most Significant Bit (MSB) first transmission. The ZL38002 microport automatically accommodates both schemes for normal data bytes. However, to ensure timely decoding of the R/W and address information, the Command/Address byte is defined differently for Intel and Motorola/National operations. Refer to the relative timing diagrams of Figure 6 and Figure 7. Receive data bits are sampled on the rising edge of SCLK while transmit data is clocked out on the falling edge of SCLK. Detailed microport timing is shown in Figure 13 and Figure 14.
4.0
Bootload Process and Execution from RAM
A bootloadable program RAM (BRAM) is available on the ZL38002 to support factory-issued software upgrades to the built-in algorithm. To make use of this bootload feature, users must include 4096 X 8 bits of memory in their microcontroller system (i.e., external to the ZL38002), from which the ZL38002 can be bootloaded. Registers and program data are loaded into the ZL38002 in the same fashion via the serial microport. Both employ the same command / address / data byte specification described in the previous section on serial microport. Either intel or motorola mode may be transparently used for bootloading. There are also two registers relevant to bootloading (BRC=control and SIG=signature, see Register Summary). The effect of these register values on device operation is summarized in Table 5. Bootload mode is entered and exited by writing to the bootload bit in the Bootload RAM Control (BRC) register at address 3fh (see Register Summary). During bootload mode, any serial microport "write" (R/W command bit =0) to an address other than that of the BRC register will contribute to filling the program BRAM. Call these transactions "BRAM-fill" writes. Although a command/address byte must still precede each data byte (as described for the serial microport), the values of the address fields for these "BRAM-fill" writes are ignored (except for the value 3fh, which designates the BRC register.) Instead, addresses are internally generated by the ZL38002 for each "BRAM-fill" write. Address generation for "BRAM-fill" writes resumes where it left off following any read transaction while bootload mode is enabled. The first 4096 "BRAM-fill" writes while bootload is enabled will load the memory, filling the BRAM and ignoring further writes. Before bootload mode is disabled, it is recommended that users then read back the value from the signature register (SIG) and compare with the one supplied by the factory along with the code. Equality verifies that the correct data has been loaded. The signature calculation uses an 8-bit MISR which only incorporates input from "BRAM-fill" writes. Resetting the bootload bit (C2) in the BRC register to 0 (see Register Summary) exits bootload mode, resetting the signature (SIG) register and internal address generator for the next bootload. A hardware reset (RESET=0) similarly returns the ZL38002 to the ready state for the start of a bootload.
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FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM
Data Sheet
BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM) R/W W BRC Register Bits C3C2C1C0 X100 R 0x xxxxb Reads back "data" = SIG reg value. - Bootload frozen; BRAM contents are NOT affected. Address 3fh (= 1 1 1 1 1 1 b) other than 3fh 1x xxxxb Data Writes "data" to BRC reg. - Bootload frozen; BRAM contents are NOT affected. Writes "data" to next byte in BRAM (bootloading.) Reads back "data" = BRC reg value. - Bootload frozen; BRAM contents are NOT affected.
W R
NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs) BRC Register Bits C3C2C1C0 X000 R/W W (= a5 a4 R (= a5 a4 Address any
a3 a2 a1 a0
Data Writes "data" to corresponding DREG. b) Reads back "data" = corresponding DREG value. b)
any
a3 a2 a1 a0
PROGRAM EXECUTION MODES C3C2C1C0 0000 Execute program in ROM, bootload mode disabled. - BRAM address counter reset to initial (ready) state. - SIG register reseeded to initial (ready) state Execute program in ROM, while bootloading the RAM. - BRAM address counter increments on microport writes (except to 3fh) - SIG register recalculates signature on microport writes (except to 3fh) Execute program in RAM, bootload mode disabled. - BRAM address counter reset to initial (ready) state. - SIG register reseeded to initial (ready) state - INVALID -
C3C2C1C0 0100
C3C2C1C0 1000
C3C2C1C0 1100
Note: bits C1 C0 are reserved, and must be set to zero.
Table 5 - Bootload RAM Control (BRC) Register States
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Data Sheet
To begin execution from the RAM once the program has been loaded, the bootload mode must be disabled (BOOT bit, C2=0) and execution from RAM enabled (RAM_ROMb bit, C3=1) by setting the appropriate bits in the BRC register. During the bootload process, however, ROM program execution (RAM_ROMb bit, C3=0) should be selected. See Table 5 for the effect of the BRC register settings on Microport accesses and on program execution. Following program loading and enabling of execution from RAM, it is recommended that the user set the software reset bit in the Main Control (MC) register, to ensure that the device updates the default register values to those of the new program in RAM. Note: it is important to use a software reset rather than a hardware (RESET=0) reset, as the latter will return the device to its default settings (which includes execution from program ROM instead of RAM.) To verify which code revision is currently running, users can access the Firmware Revision Code (FRC) register (see Register Summary). This register reflects the identity code (revision number) of the last program to run register initialization (which follows a software or hardware reset.)
COMMAND/ADDRESS
DATA INPUT/OUTPUT
DATA 1
R/W A0
A1 A2 A3 A4 A5
X
D0 D1 D2 D3 D4 D5 D6 D7
SCLK
CS

This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38002. The ZL38002: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high. A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 6 bits - Addressing Data 1 bit - Unused
Figure 8 - Serial Microport Timing for Intel Mode 0
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Data Sheet
COMMAND/ADDRESS
DATA INPUT
DATA 2 Receive
R/W A5 A4 A3 A2 A1 A0
X
D7 D6 D5 D4 D3 D2 D1 D0 DATA OUTPUT
DATA 1 Transmit
High Impedance
D7 D6 D5 D4 D3 D2 D1 D0
SCLK
CS
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38002. The ZL38002: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high. A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 6 bits - Addressing Data 1 bit - Unused
Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire
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5.0 Register Summary
Data Sheet
Any register not described in the following section should be labels reserved for internal use. CPU Access R/W R/W Read R/W R/W R/W Read R/W R/W R/W R/W R/W R/W R/W Read Read R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Read Read Read Reset Value 00H 00H 00H A1H 08H A6H 80H 04H 00H 88H 08H 6DH 00H 00H 00H 80H 3EH 3DH 06H 96H 04H 80H 21H 2AH AAH 01H 00H 00H 00H 00H Send (Sin) Peak Detect Register 1 (SPDR1) Send (Sin) Peak Detect Register 2 (SPDR2) Send Error Peak Detect Register 1 (SEPDR1) Send Error Peak Detect Register 2 (SEPDR2)
Address 00H 01H 02H 03H 04H 05H 07H 08H 09H 12H 1CH 1DH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 30H 31H 32H 34H 35H 36H 37H 38H 39H
Page 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description Main Control Register 1 (MCR1) Main Control Register 2 (MCR2) Status Register (SR) DC Offset Register High Pass Filter Constant Register (FLTSH) Mu Constant Bootload RAM Signature Register (SIG) Slow Adaptation Threshold Register 1 (SATR1) Slow Adaptation Threshold Register 2 (SATR2) Automatic Sout Gain Reduction (SoutGR) Customer Gain Control Register 1 (CGCR1) Customer Gain Control Register 2 (CGCR2) Receive Gain Control Register (RGCR) Acoustic Echo Canceller Control Register (AECCR) Acoustic Echo Canceller Status Register 1 (ARCSR1) Acoustic Echo Canceller Status Register 2 (AECSR2) Acoustic LMS Filter Length Register 1 (ALMSFR1) Acoustic LMS Filter Length Register 2 (ALMSFR2) Decay Step Size Control Register (DSSCR) Decay Step Number Register (DSNR) Near-End Speech Detection Threshold 1 (NESDT1) Near-End Speech Detection Threshold 2 (NESDT2) Double-Talk Hand-Over Time 1 (DTHOT1) Double-Talk Hand-Over Time 2 (DTHOT2) Automatic Rout Gain Reduction Register (RoutGR) NLP Threshold Register
Table 6 - Address Map
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Address 3AH 3BH 3CH 3DH 3FH 1AH 1BH 3AH 3BH 1CH 1DH 15H 17H CPU Access Read Read Read Read R/W Read Read Read Read R/W R/W R/W R/W Page 0 0 0 0 0/1/2/3 1 1 1 1 2 2 3 3 Reset Value 00H 00H 00H 10H 08H 00H 00H 00H 00H 00H 08H 20H 20H Description
Data Sheet
Receive (Rout) Peak Detect Register 1 (RPDR1) Receive (Rout) Peak Detect Register 2 (RPDR2) Adaptation Speed Register 1 (ASR1) Adaptation Speed Register 2 (ASR2) BRC Bootload RAM Control Register (BRCR) Noise Level R Path Register 1 (NLRPR1) Noise Level R Path Register 2 (NLRPR2) Noise Level S Path Register 1 (NLSPR1) Noise Level S Path Register 2 (NLSPR2) AGC Gain Register 1 (AGCGR1) AGC Gain Register 2 (AGCGR2) Noise Threshold for Noise Reduction Register (NRTH) Minimum Noise Reduction Level Register(Beta)
Table 6 - Address Map (continued)
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6.0 Register Definitions
Data Sheet
Read/Write Page 0, Address: 00H Reset Value: 00H
7
LIMIT
6
MUTE_R
5
MUTE_S
4
BYPASS
3
NB-
2
AGC-
1
AH-
0
RESET
Bit 7 6 5 4 3 2 1 0
Name LIMIT MUTE_R MUTE_S BYPASS NBAGCAHRESET
Description When high, Rin and Sin signals are limited to 0.25 in amplitude. When low, no limit is imposed on the inputs. When high, the Rin path is muted to quiet code (after the NLP) and when low the Rin path is not muted. When high, the Sin path is muted to quiet code (after the NLP) and when low the Sin path is not muted. When high, the Send and Receive paths are transparently by-passed from input to output and when low the Send and Receive paths are not bypassed. When high, Narrowband signal detectors in Rin and Sin paths are disabled and when low the signal detectors are enabled. When high, AGC is disabled and when low AGC is enabled. When high, the Howling detector is disabled and when low the Howling detector is enabled. When high, the power initialization routine is executed presetting all registers to default values. This bit automatically clears itself to'0' when reset is complete. Register Table 1 - Main Control Register 1 (MC1)
Read/Write Address: 01H Reset Value: 00H
7
SHFT
6
Reserved
5
Reserved
4
NRdis
3
NSUP3
2
NSUP2
1
NSUP1
0
NSUP0
Bit 7
Name SHFT
Description When high and in 16-bit linear mode, this bit enables shift right by 2 on inputs Sin, Rin, and shift left by 2 on outputs Sout, Rout, for codec. If not in 16-bit linear mode for both I/O ports, this bit is ignored. When low, =default, no shift. Reserved: Must be set to low Reserved: Must be set to low Register Table 2 - Main Control Register 2 (MC2)
6 5
Reserved Reserved
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Read/Write Address: 01H Reset Value: 00H
7
SHFT
Data Sheet
6
Reserved
5
Reserved
4
NRdis
3
NSUP3
2
NSUP2
1
NSUP1
0
NSUP0
Bit 4 3-0
Name NRDIS NSUP
Description When high, noise reduction is disabled. When low, noise reduction is enabled. Noise Suppression Threshold - Any value below this threshold in the send path will be suppressed (reset) Register Table 2 - Main Control Register 2 (MC2)
Read/Write Page 0, Address:02H Reset Value: 00H
7
Reserved
6
Reserved
5
HFLAG
4
Reserved
3
Reserved
2
Reserved
1
NB
0
NBR
Bit 7-6 5
Name Reserved HFLAG Reserved: Must be set to low
Description
False howling detect bit.'1' indicates' false howling' detected (music or sinusoidal match).'0' indicates no 'false howling', i.e. howling is not ruled out (by any matches to music or speech). The final howling decision is in bit 5 of ASR (HWLNG). Reserved: Must be set to low This bit indicates a LOGICAL-OR of status bits NBR + NBS (from ASR register). When high, a narrowband signal has been detected in the Receive (Rin/Rout) path.
4-2 1 0
Reserved NB NBR
Register Table 3 - Acoustic Echo Canceller Status Register
Read/Write Page 0, Address: 03H Reset Value: 60H
7
Reserved
6
Reserved
5
Reserved
4
DC4
3
DC3
2
DC2
1
DC1
0
DC0
Bit 7-5 4-0
Name Reserved DC4-DC0 Reserved: Must be set to low
Description
DC offset value in mute condition. Register Table 4 - DC Offset Register
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Data Sheet
Read/Write Page 0, Address: 04H Reset Value: A1H
7
FR2
6
FR1
5
FR0
4
FS4
3
FS3
2
FS2
1
FS1
0
FS0
Bit 7-5 4-0
Name FR2-FR0 FS4-FS0
Description These four bits control the cut-off frequency of HPF at Rin. These four bits control the cut-off frequency of HPF at Sin.
3 dB frequency and bit 0-4 for Sin 00: 2 KHz; 08: 2.65 Hz; 10: 3 KHz; 18: 3.6 Hz 01: 820 Hz; 09: 1.1 KHz; 11: 1.2 KHz; 19: 1.6 KH 02: 350 Hz; 0A: 450 Hz; 12: 580 Hz; 1A: 700 Hz 03: 160 Hz; 0B: 200 Hz; 13: 250 Hz; 1B: 300 Hz 04: 80 Hz; 0C: 100 Hz; 14: 125 Hz; 1C: 150 Hz 05: 40 Hz; 0D: 50 Hz; 15: 60 Hz; 1D: 70 Hz 06: 20 Hz; 0E: 25 Hz; 16: 30 Hz; 1E: 38 Hz 07: 10 Hz; 0F: 14 Hz; 17: 15 Hz; 1F: 18 Hz
3dB frequency and bit 5-7 for Rin 0: 2 KHz; 1; 820 Hz; 2: 350 Hz; 3: 160 Hz; 4: 80 Hz; 5: 40 Hz; 6: 20 Hz; 7: 10 Hz
Register Table 5 - High Pass Filter Constant Register (FLTSH)
Read/Write Page 0, Address:05H Reset Value: 08H
7
RESV
6
RESV
5
MU5
4
MU4
3
MU3
2
MU2
1
MU1
0
MU0
Bit 7-0
Name MU5-0
Description This register allows the user to program control the adaptation speed. This register allows a maximum value of 3Fh. The default value is 08h corresponding to decimal value of 2.0. Decimal value of 1.0 is 04h. Lower values correspond to slower adaptation speed. Reserved. Write'0'. Register Table 6 - Mu Constant Register
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Data Sheet
Read/Write Page 0, Address: 07H Reset Value: FFH
7
SIG7
6
SIG6
5
SIG5
4
SIG4
3
SIG3
2
SIG2
1
SIG1
0
SIG0
Bit 7-0
Name
Description This register provides the signature of the bootloaded data to verify error-free delivery into the device. Note: this register is only accessible if BOOT bit is high (bootload mode enabled) in the above BRC register. While bootload is disabled, the register value is held constant at its reset seed value of FFh.
SIG7-0
Register Table 7 - Bootload RAM Signature Register (SIG)
Read/Write Page 0, Address: 09H Reset Value: 04H
7
SAT15
6
SAT14
5
SAT13
4
SAT12
3
SAT11
2
SAT10
1
SAT9
0
SAT8
Read/Write Page 0, Address: 08H Reset Value: 80H
7
SAT7
6
SAT6
5
SAT5
4
SAT4
3
SAT3
2
SAT2
1
SAT1
0
SAT0
Bit 15-0
Name SAT15-SAT0
Description Threshold for deciding low adaptation speed. 8000h = 1.0.
Register Table 8 - Slow Adaptation Threshold Registers (SATR1) & (SATR2)
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Data Sheet
Read/Write Page 0, Address: 12H Reset Value: 00H
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0 SoutGR
Bit 7-1 0
Name Reserved SoutGR Reserved: Must be set to low
Description
This bit will provide an automatic signal reduction on Sout by 12 dB (far-end speaker) when double talk is present with this bit set to 1. Register Table 9 - Sout Gain Reduction (SoutGR)
Read/Write Page 0, Address: 1DH Reset Value: 08H
15
Reserved
14
Reserved
13
Reserved
12
Reserved
11
XRAMGain3
10
XRAMGain2
9
XRAMGain1
8
XRAMGain0
Read/Write Page 0, Address: 1CH Reset Value: 88H
7
SoutGain3
6
SoutGain2
5
SoutGain1
4
SoutGain0
3
SinGain3
2
SinGain3
1
SinGain3
0
SinGain3
Bit 15-12 11-8 7-4 3-0
Name Reserved XRAMGain3-0 SoutGain3-0 SinGain3-0 Reserved: Must be set to low
Description
Gain control for ROUT to Xram, range from -24 dB to 21 dB. (1111=+21dB, 0000=-24 dB) Gain control for SOUT, range from -24 dB to 21 dB. (1111=+21dB, 0000=24 dB) Gain control for SIN, range from -24 dB to 21 dB. (1111=+21dB, 0000=24 dB)
Register Table 10 - Customer Gain Control Registers (CGCR1) & (CGCR2)
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Data Sheet
Read/Write Page 0, Address: 20H Reset Value: 00H
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
G3
2
G2
1
G1
0
G0
Bit 7-4 3 2 1 0
Name Reserved G3 G2 G1 G0 Reserved: Must be set to low
Description
User Gain Control on Rin/Rout path. (Tolerance of gain values: +/- 0.15 dB
Gain Code: G4-G0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh
Gain(dB) data sheet -24 -21 -18 -15 -12 -9 -6 -3 +0 +3 +6 +9 +12 +15 +18 +21
Gain(dB) actual -24.08 -21.31 -18.06 -14.91 -12.04 -9.08 -6.02 -3.06 +0 +3.01 +5.99 +9.01 +12.01 +15.03 +18.03 +21.05
Register Table 11 - Receive Gain Control (RCGR)
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Read/Write Page 0, Address: 21H Reset Value: 00H
7
Reserved
Data Sheet
6
ASC-
5
NLP-
4
INJ-
3
HPF-
2
HCLR
1
ADAPT-
0
ECBY
Bit 7 6 5 4 3
Name Reserved ASCNLPNJHPFReserved: Must be set to low
Description
When high, internal adaptation speed control is disabled. When low, internal adaptation speed control is enabled. When high, the non-linear processor in the Sin/Sout path is disabled. When low, the non-linear processor in the Sin/Sout path is enabled. When high, the noise filtering process is disabled in the NLP. When low, the noise filtering process is enabled in the NLP. When high, the offset nulling filter is bypassed in the Sin/Sout path. When low, the offset nulling filter in the Sin/Sout path is active and will remove DC offset on the Rin input signal. When high, the H register in the adaptive filter is cleared. When low, the H register is not cleared When high, echo canceller adaptation is disabled. When low, the echo canceller adapts to the echo path characteristics. When high, the echo estimate from the adaptive filter is not subtracted from the Send path. When low, the echo estimate is subtracted from the Send path.
2 1 0
HCLR ADAPTECBY
Register Table 12 - Acoustic Echo Canceller Control Register (AECCR)
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Data Sheet
Read Page 0, Address: 22H Reset Value: 00H
7
ACMUTH
6
ACMUND
5
HWLNG
4
NLPUTH
3
NLPDCW
2
DT
1
NB
0
NBS
Bit 7 6 5
Name ACMUTH ACMUND HWLNG
Description Energy comparison for mu value.'1' indicates enough echo suppression. When low, indicates that the Rin/Rout Receive path has no active signal. When high indicates that howling is occurring in the loop. A related 'false howling' bit (HFLAG) in bit 5 of LSR is created as part of the howling-detect decision making. Peak comparison with NLP up threshold.'1' indicates not enough echo suppression. When high indicates that the NLP is activated. When high, double-talk is present. This bit indicates a LOGICAL-OR of status bits NBS + NBR (from LSR register). When high, a narrowband signal has been detected in the Send (Sin/Sout) path.
4 3 2 1 0
NLPUTH NLPDC DT NB NBS
Register Table 13 - STATUS Acoustic Echo Canceller Status Register (AECSR1)
Read Page 0, Address: 23H Reset Value: 00H
7
Reserved
6
Reserved
5
Reserved
4
DHCLR
3
ACMUFL
2
ACMULOW
1
ACMUNSP
0
NLPDCLD
Bit 7-4 4
Name Reserved DHCLR
Description
Indicate the divergence of adaptation. "1" indicates that strong divergence occurs with error energy is at least double the input signal energy. Reserved (anything written on it will be overwritten by temporary variable in the program).
3 2 1 0
ACMUFL Reserved ACMUNSP Reserved
Adaptation floor decision. '1' indicates the reference is below the adaptation floor, no adaptation.
Indicates strong near-end speech.
Register Table 14 - Acoustic Echo Canceller Status register 2 (AECSR2)
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Data Sheet
Read/Write Page 0, Address: 25H Reset Value: 3EH
15
L7
14
L6
13
L5
12
L5
11
L4
10
L3
9
L2
8
L1
Read/Write Page 0, Address: 24H Reset Value: 80H
7
L0
6
F6
5
F5
4
F4
3
F3
2
F2
1
F1
0
F0
Bit 6-0 15-7
Name F6-F0 L7-L0
Description Allows the acoustic LMS filter length to be reduced. The register value is in terms of milliseconds. Maps to Rout limiter value, Limit = 0L8L7L6 L5L4L3L2 L1L000 0000, Range: 040h - 7FC0h, plus 00h point value. Default: 1F40h
Register Table 15 - Acoustic LMS Filter Length Registers (ALMSFR1) & (ALMSFR2)
Read/Write Page 0, Address: 26H Reset Value: 3DH
7
L4
6
L3
5
L2
4
L1
3
L0
2
SSC2
1
SSC1
0
SSC0
Bit 7-3
Name L4-L0
Description Sout Limit Value: Stores the variable limit for Sout. The interpretation of these bits is not direct: 00111 maps to default value = 1F40h. Limit level = 0L4L3L2 L1L011 0100 0000, range: 0340h - 7F40h. Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU.
2-0
SSC2-SSC0
Register Table 16 - Decay Step Size Control Register (DSSCR)
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Read/Write Page 0, Address: 27H Reset Value: 06H
7
NS7
Data Sheet
6
NS6
5
NS5
4
NS4
3
NS3
2
NS2
1
NS1
0
NS0
Bit 7-0
Name NS7-NS0
Description Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a period of SS taps (see SSC2-0).
Register Table 17 - Decay Step Number Register (DSNR)
Amplitude of MU FIR Filter Length (896 taps) 1.0 Step Size (SS)
2-16
Time Number of Steps (NS7-0)
The Exponential Decay registers (Decay Step Number and Decay Step Size) allow the LMS adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the echo response is known to have a roughly exponential decay of the echo impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the adaptive filter. Note that in the following register descriptions, one tap is equivalent to 125 ms. SSC2-0 Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4 x2SSC2-0. For example; If SSC2-0 = 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default value of SSC2-0 is 05h. Sout Limit Value: Stores the variable limit for Sout. The interpretation of these bits is not direct: 00111 maps to default value = 1F40h. Limit level = 0L4L3L2 L1L011 0100 0000 , range: 0340h - 7F40h. Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a period of SS taps (see SSC2-0). The start of the exponential decay is defined as: Filter Length (896) - [Decay Step Number (NS7-0) x Step Size (SS)] where SS = 4 x2SSC2-0. For example, if NS7-0=4 and SSC2-0=4, then the exponential decay start value is 896 - [NS7-0 x SS] = 896 - [4 x (4x24)] = 640 taps for a filter length of 896 taps.
L4-0
NS7-0
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Data Sheet
Read/Write Page 0, Address: 29H Reset Value: 04H
15
MUURAT15
14
MUURAT14
13
MUURAT13
12
MUURAT12
11
MUURAT11
10
MUURAT10
9
MUURAT9
8
MUURAT8
Read/Write Page 0, Address: 28H Reset Value: 96H
7
MUURAT7
6
MUURAT6
5
MUURAT15
4
MUURAT4
3
MUURAT3
2
MUURAT2
1
MUURAT1
0
MUURAT0
Bit 15-0
Name
MUURAT15MUURAT0
Description Threshold for deciding near end speech (mu = 0). 1000h = 1.0.
Register Table 18 - Near-End Speech Detection Threshold Registers (NESDT1) & (NESDT2)
Read/Write Page 0, Address: 31H Reset Value: 04H
15
DTTH2
14
DTTH1
13
DTTH1
12
DTHOT12
11
DTHOT11
10
DTHOT10
9
DTHOT9
8
DTHOT8
Read/Write Page 0, Address: 30H Reset Value: 96H
7
DTHOT7
6
DTHOT6
5
DTHOT5
4
DTHOT4
3
DTHOT3
2
DTHOT2
1
DTHOT1
0
DTHOT0
Bit 13-15 12-0
Name
DTTH2DTTH0
Description Double Talk Threshold- in 6 dB increments from -30 dB to (0h = -30 dB, 7h = +12 dB Double-Talk hand-over time
DTHOT12-DTHOT0
Register Table 19 - Near-End Speech Detection Threshold Registers (DTHOT1) & (DTHOT2)
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Data Sheet
Read/Write Page 0, Address: 32H Reset Value: 2AH
7
RESERVED
6
RESERVED
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
RESERVED
0
RoutGR
Bit 0
Name
Description This bit will provide an automatic signal reduction on Rout by 12 db when double talk is present with this bit set to 1. Figure 10 - Automatic Rout Gain Reduction (RoutGR)
RoutGR
Read/Write Page 01, Address: 35H Reset Value: 01H
15
NLPTH15
14
NLPTH14
13
NLPTH13
12
NLPTH12
11
NLPTH11
10
NLPTH10
9
NLPTH9
8
NLPTH8
Read/Write Page AA, Address: 34H Reset Value: AAH
7
NLPTH7
6
NLPTH6
5
NLPTH15
4
NLPTH4
3
NLPTH3
2
NLPTH2
1
-NLPTH1
0
NLPTH0
Bit 15-0
Name NLPTH15NLPTH0
Description This register allows the user to program the level of the Non-Linear Processor Threshold. The 16 bit 2's complement linear value defaults to 1AAh. The maximum value is 7FFFh = 0.9999. Higher value corresponds to higher threshold. The high byte is in Register 2 and the low byte is in Register 1. Register Table 20 - NLP Threshold Register
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Data Sheet
Read/Write Page 0, Address: 37H Reset Value: 00H
15
SIPD15
14
SIPD14
13
SIPD13
12
SIPD12
11
SIPD11
10
SIPD10
9
SIPD9
8
SIPD8
Read/Write Page 0, Address: 36H Reset Value: 00H
7
SIPD7
6
SIPD6
5
SIPD15
4
SIPD4
3
SIPD3
2
SIPD2
1
SIPD1
0
SIPD0
Bit 15-0
Name SIPD15-SIPD0
Description These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level at reference point S1 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 21 - Send (Sin) Peak Detect Registers (SPDR1) & (SPDR2)
Read/Write Page 0, Address: 39H Reset Value: 00H
15
SEPD15
14
SEPD14
13
SEPD13
12
SEPD12
11
SEPD11
10
SEPD10
9
SEPD9
8
SEPD8
Read/Write Page 0, Address: 38H Reset Value: 00H
7
SEPD7
6
SEPD6
5
SEPD15
4
SEPD4
3
SEPD3
2
SEPD2
1
SEPD1
0
SEPD0
Bit 15-0
Name SEPD15-SEPD0
Description These peak detector registers allow the user to monitor the error signal peak level in the Send path at reference point S2 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 22 - Send Error Peak Detect Registers (SEPDR1) & (SEPDR2)
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Data Sheet
Read/Write Page 0, Address: 3BH Reset Value: 00H
15
ROPD15
14
ROPD14
13
ROPD13
12
ROPD12
11
ROPD11
10
ROPD10
9
ROPD9
8
ROPD8
Read/Write Page 0, Address: 3AH Reset Value: 00H
7
ROPD7
6
ROPD6
5
ROPD15
4
ROPD4
3
ROPD3
2
ROPD2
1
ROPD1
0
ROPD0
Bit 15-0
Name ROPD15ROPD0
Description These peak detector registers allow the user to monitor the receive out signal (Rout) peak signal level at reference point R1 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 23 - Receive (Rout) Peak Detect Registers (RPDR1) & (RPDR2)
Read/Write Page 0, Address: 3DH Reset Value: 10H
15
A_AS15
14
A_AS14
13
A_AS13
12
A_AS12
11
A_AS11
10
A_AS10
9
A_AS9
8
A_AS8
Read/Write Page 0, Address: 3CH Reset Value: 00H
7
A_AS7
6
A_AS6
5
A_AS5
4
A_AS4
3
A_AS3
2
A_AS2
1
A_AS1
0
A_AS0
Bit 15-0
Name A_AS15-0
Description Actual mu sent to acoustic LMS. This register is where we can feed externally calculated mu value. This register allows the user to program control the adaptation speed. The default value is 1000h corresponding to decimal value of 2.0. The high byte is in Register 2 and the low byte is in Register 1. Smaller values correspond to slower adaptation speed.
Register Table 24 - Adaptation Speed Registers (ASR1) & (ASR2)
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Data Sheet
Read/Write Page 0/1/2/3, Address: 3FH Reset Value: 00H
7
-
6
-
5
-
4
-
3
ROM/RAM
2
BOOT BIT
1
PAGEH
0
PAGEL
Bit 7-4 3 2 1 0
Name Unused RAM/ROM BOOT BIT PAGE H PAGE L Must be set to 0
Description
When high, device executes from RAM. When low, device executes from ROM. When high, puts device in bootload mode. When low, bootload is disabled. Controls the register page being accessed by address 00h-3Fh. 00 = page 0 (default), 01 = page 1, 10= page 2, 11 = page 3
Register Table 25 - BRC Bootload RAM Control Register (BRCR)
Read/Write Page 1, Address: 1BH Reset Value: 10H
15
NLVRL15
14
NLVRL14
13
NLVRL13
12
NLVRL12
11
NLVRL11
10
NLVRL10
9
NLVRL9
8
NLVRL8
Read/Write Page 1, Address: 1AH Reset Value: 00H
7
NLVRL7
6
NLVRL6
5
NLVRL5
4
NLVRL4
3
NLVRL3
2
NLVRL2
1
NLVRL1
0
NLVRL0
Bit 15-0
Name NLVRL15-0
Description Estimated noise level in R path.
Register Table 26 - Noise Level Registers R Path (NLRPR1) & (NLRPR2)
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Data Sheet
Read/Write Page 1, Address: 3BH Reset Value: 00H
15
NLVSL15
14
NLVSL14
13
NLVSL13
12
NLVSL12
11
NLVSL11
10
NLVSL10
9
NLVSL9
8
NLVSL8
Read/Write Page 1, Address: 3AH Reset Value: 00H
7
NLVSL7
6
NLVSL6
5
NLVSL5
4
NLVSL4
3
NLVSL3
2
NLVSL2
1
NLVSL1
0
NLVSL0
Bit 15-0
Name NLVRL15-0
Description Estimated noise level in S path.
Register Table 27 - Noise Level S Path Registers (NLSPR1) & (NLSPR2)
Read/Write Page 2, Address: 1DH Reset Value: 08H
15
AGCGN15
14
AGCGN14
13
AGCGN13
12
AGCGN12
11
AGCGN11
10
AGCGN10
9
AGCGN9
8
AGCGN8
Read/Write Page 2, Address: 1CH Reset Value: 00H
7
AGCGN7
6
AGCGN6
5
AGCGN5
4
AGCGN4
3
AGCGN3
2
AGCGN2
1
AGCGN1
0
AGCGN0
Bit 15-0
Name AGCGN15-0 AGC gain value (1=4000h)
Description
Register Table 28 - AGC Gain Register (AGCGR1) & (AGCGR2)
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ZL38002
Data Sheet
Read/Write Page 3, Address: 15H Reset Value: 20H
7
NRTH7
6
NRTH6
5
NRTH5
4
NRTH4
3
NRTH3
2
NRTH2
1
NRTH1
0
NRTH0
Bit 7-0
Name NRTH7-0
Description This register scales the noise threshold for noise reduction.
Register Table 29 - Noise Threshold for Noise Reduction Register (NRTH)
Read/Write Page 3, Address: 17H Reset Value: 20H
7 6 5 4 3 2 1 0
BETA7
BETA6
BETA5
BETA4
BETA3
BETA2
BETA1
BETA0
Bit 7-0
Name BETA7-0
Description This register sets the minimum noise reduction for each sample. Register Table 30 - Noise reduction Register
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7.0 Electrical Characteristics
Data Sheet
Absolute Maximum Ratings* Parameter 1 2 3 4 5 Supply Voltage Input Voltage Output Voltage Swing Continuous Current on any digital pin Storage Temperature Symbol VDD-VSS Vi Vo Ii/o TST -65 Min. -0.5 VSS-0.3 VSS-0.3 Max. 5.0 5.5 5.5 20 150 Units V V V mA C mW
6 Package Power Dissipation PD 90 (typ) * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 Supply Voltage Input High Voltage Input Low Voltage Operating Temperature TA Sym. VDD Min. 2.7 1.4 VSS -40 Typ. 3.3 Max. 3.6 VDD 0.4 +85 Units V V V C Test Conditions
Echo Return Limits Characteristics 1 Acoustic Echo Return Min. Typ. Max. 6 Units dB Test Conditions Measured from Rout -> Sin (using the Customer Gain Control registers)
DC Electrical Characteristics*- Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Standby Supply Current: 1 2 3 4 5 6 7 8 9 Operating Supply Current: Input HIGH voltage Input LOW voltage Input leakage current High level output voltage Low level output voltage High impedance leakage Output capacitance Input capacitance Sym. ICC IDD VIH VIL IIH/IIL VOH VOL IOZ Co Ci 1 10 8 0.8VDD 0.4V 10 0.1 0.7VDD 0.3VDD 10 Min. Typ. 3 20 Max. 70 Units A mA V V A V V A pF pF VIN=VSS to VDD IOH=2.5 mA IOL=5.0 mA VIN=VSS to VDD Conditions/Notes RESET = 0 RESET = 1, clocks active
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. *DC Electrical Characteristics are over recommended temperature and supply voltage.
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics - Serial Data Interfaces - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MCLK Frequency BCLK/C4i Clock High BCLK/C4i Clock Low BCLK/C4i Period SSI Enable Strobe to Data Delay (first bit) SSI Data Output Delay (excluding first bit) SSI Output Active to High Impedance SSI Enable Strobe Signal Setup SSI Enable Strobe Signal Hold SSI Data Input Setup SSI Data Input Hold ST-BUS/GCI F0i Setup ST-BUS/GCI F0i Hold ST-BUS/GCI Data Output delay ST-BUS/GCI Output Active to High Impedance ST-BUS/GCI Data Input Hold time ST-BUS/GCI Data Input Setup time Sym. fCLK tBCH, tC4H tBLL, tC4L tBCP tSD tDD tAHZ tSSS tSSH tDIS tDIH tF0iS tF0iH tDSD tASHZ tDSH tDSS Min. 19.15 90 90 240 80 80 80 10 15 10 15 20 20 80 80 20 20 150 150 tBCP -15 tBCP -10 7900 Typ. Max. 20.5 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL = 150 pF CL = 150 pF CL = 150 pF CL = 150 pF CL = 150 pF Test Notes
Timing is over recommended temperature and power supply voltages.
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AC Electrical Characteristics - Microport Timing Characteristics 1 2 3 4 5 6 7 8 9 10 Input Data Setup Input Data Hold Output Data Delay Serial Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Setup-Intel CS Setup-Motorola CS Hold CS to Output High Impedance Sym. tIDS tIDH tODD tSCP tSCH tSCL tCSSI tCSSM tCSH tOHZ 500 250 250 200 100 100 100 Min. 30 30 100 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns CL = 150 pF CL = 150 pF
Data Sheet
Test Notes
Timing is over recommended temperature range and recommended power supply voltages.
Characteristic CMOS reference level Input HIGH level Input LOW level Rise/Fall HIGH measurement point Rise/Fall LOW measurement point
Symbol VCT VH VL VHM VLM
CMOS Level 0.5*VDD 0.9*VDD 0.1*VDD 0.7*VDD 0.3*VDD
Units V V V V V
Table 7 - Reference Level Definition for Timing Measurements
T=1/fCLK MCLK (I)
VH
VCT
VL
Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions)
Figure 11 - Master Clock - MCLK
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Zarlink Semiconductor Inc.
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Bit 7 Sout/Rout (O) tDSD C4i (I)
VH
Data Sheet
Bit 6 VCT tC4H tASHZ
VCT
VL
tF0iS tF0iH F0i (I)
VH VL
input sampled
tC4L VCT
start of frame
tDSS tDSH VCT
Rin/Sin (I)
VH VL
Bit 7
Bit 6
Figure 12 - GCI Data Port Timing
Bit 7 Sout/Rout (O) tDSD C4i (I)
VH
input sampled
Bit 6 VCT tC4H tASHZ
VL
VCT tF0iS tF0iH tC4L
F0i (I)
VH VL
start of frame
VCT tDSS tDSH
Rin/Sin (I)
VH
VCT
VL
Bit 7
Bit 6
Figure 13 - ST-BUS Data Port Timing
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Zarlink Semiconductor Inc.
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Bit 7 Sout/Rout
(O)
Data Sheet
Bit 6
Bit 5 VCT
tSD BCLK (I)
VH
tDD
tBCH
tAHZ
VCT tSSS tBCP
input sampled
VL
tBCL
tSSH
ENA1 (I) or ENA2 (I)
VH VL
VCT tDIS tDIH
start of frame
VH
Rin/Sin (1)
VCT
VL
Bit 7 Notes: O. CMOS output
Bit 6
Bit 5 (see Table 8 for symbol definitions)
I. CMOS input (5 V tolerant)
Figure 14 - SSI Data Port Timing
DATA INPUT DATA1
(I,O)
DATA OUTPUT VCT
tIDS tIDH SCLK (I)
VH
tSCH
tODD
tOHZ
VCT
VL
tCSSI CS (I)
VH
tSCL
tSCP
tCSH
VCT
VL
Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions)
Figure 15 - INTEL Serial Microport Timing
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Data Sheet
DATA2 (I) (Input)
VH VL
VCT tIDS tIDH tSCH tSCP
SCLK (I)
VH
VCT
VL
tCSSM CS (I)
VH
tSCL
tCSH
VCT
VL
tODD DATA1 (O) (Output)
tOHZ
VCT
Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions)
Figure 16 - Motorola Serial Microport Timing
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Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
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Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
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